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Interdisciplinary Initiatives Program Seed Grant: Hardware/Algorithm Co-Design for Implantable Brain-Computer Interfaces

Seed Grants
Awarded in 2020

Interdisciplinary Initiatives Program Round 10 - 2020

Boris Murmann, Electrical Engineering
Jaimie Henderson, Neurosurgery
Krishna Shenoy, Electrical Engineering

Millions of people worldwide suffer from motor-related neurological injury and disease. To restore movement via prosthetic limbs or to guide computer cursors to restore communication, research over the past two decades has led to the successful demonstration of intracortical braincomputer interfaces (iBCIs). What was merely “science fiction” in the past has now matured into compelling proof-of-concept systems with human FDA pilot clinical trials at Stanford.

As modern iBCI systems continue to improve and march toward clinical deployment, the requirements for the underlying hardware and software systems become increasingly challenging. The fundamental issue lies in the immense amount of data (typically on the order of megabits/second) that must be processed in real time. Additionally, the complexity of the computing algorithms has been growing rapidly to maximize the decoding performance. In today’s lab systems, these issues are being sidestepped by cable-tethering and running the decoding algorithms on desktop-size computers. However, it is clear that a much smaller form factor is required for practical end-game solutions.

The proposed project considers the synergistic interplay between the iBCI’s application requirements, its neuroscientific underpinnings, and leading-edge hardware design to lay the groundwork for next generation systems with untethered, wearable form factors. We recognize that computing hardware no longer delivers “automatic” performance improvements due to the end of chip technology scaling, forcing increasingly specialized architectures for each application domain. In the domain of Neuroscience/iBCi, such customizations must exploit the stochastic nature of the neural signals (the computing can be “approximate”) and hardware-algorithm codesign that leverages aggressive dimensionality reductions throughout the processing pipeline. This new data- and application-driven approach to hardware design motivates the interdisciplinary teaming for this work.

Our research will pursue three specific aims in a top-down fashion. The first is to design a suite of machine learning based decoder architectures using offline neural data sets. The second aim is to run these algorithms in real time, and with a patient in the loop, to identify solutions that show the highest performance in a practical setting. The third aim is to couple the algorithm development to the design of custom machine learning hardware that will be orders of magnitude more efficient and less bulky than current lab systems.